Iota » History » Version 11
laforge, 02/21/2016 08:17 AM
1 | 11 | laforge | h1. Iota (TWL3025) |
---|---|---|---|
2 | |||
3 | 1 | laforge | This is the Analog Baseband Chip TWL3025 |
4 | 2 | laforge | |
5 | 8 | laforge | It's very similar to its predecessors, the TWL3014 and TWL3016 devices. |
6 | |||
7 | A data sheet for the TWL3014 is available from http://www.52rd.com/bbs/Detail_RD.BBS_8719_68_1_1.html |
||
8 | but forum registration is required for download. |
||
9 | |||
10 | 7 | laforge | It consists of various functions, including |
11 | 10 | steve-m | * ADC and DAC for the GSM baseband signals |
12 | * ADC and DAC for the Voice/Audio path |
||
13 | * DAC for APC (Automatic Power Control) |
||
14 | * DAC for AFC (Automatic Frequency Control) |
||
15 | * Battery Charging Controller |
||
16 | * LDO's (Linear Power Regulators) |
||
17 | 7 | laforge | |
18 | 1 | laforge | The functions of the ABB are controlled by a register set. The register set |
19 | 7 | laforge | is available through both USP and BSP. |
20 | |||
21 | |||
22 | 10 | steve-m | h2. External Interfaces == |
23 | USP (uController Serial Port) === |
||
24 | |||
25 | 1 | laforge | This is the SPI-like control interface between DBB and the TWL3025 (ABB). |
26 | |||
27 | [[Image(Iota:twl3025_usp.png)]] |
||
28 | |||
29 | |||
30 | 10 | steve-m | h3. TSP (Timee Serial Port) |
31 | 1 | laforge | |
32 | 10 | steve-m | |
33 | It is connected to the TSP controller inside the [[HardwareCalypso]] DBB. |
||
34 | |||
35 | 9 | steve-m | The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: |
36 | 10 | steve-m | * CLK_13M is applied continuously to TWL3025 |
37 | * nTEN is in default state of high (inactive) |
||
38 | * internal CLK6.5 is in default state low |
||
39 | * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge |
||
40 | * next CLK13M falling edge starts first CLK6.5 rising edge |
||
41 | * every falling edge of CLK13M toggles CLK6.5 |
||
42 | * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) |
||
43 | * 7 bits are transferred during seven rising edges of CLK6.5 |
||
44 | * TEN stays asserted for 1 CLK13M period after last bit is transferred |
||
45 | * TEN needs to be released before next CLK13M rising edge to prevent another transfer |
||
46 | 1 | laforge | |
47 | |||
48 | 10 | steve-m | h3. BSP (Baseband Serial Port) |
49 | 7 | laforge | |
50 | 10 | steve-m | |
51 | This synchronous serial port is connected to the RIF (Radio [[InterFace]]) of the Calypso DBB. |
||
52 | |||
53 | |||
54 | h3. Debug traces |
||
55 | |||
56 | 9 | steve-m | |
57 | 1 | laforge | The chip has very tiny debug traces on a small flex-pcb around the 4 sides of the chip. |
58 | Which trace goes to which ball can be seen on this scan: http://www.steve-m.de/pictures/iota_bottom.jpg |