Iota » History » Version 13
laforge, 02/21/2016 10:26 AM
| 1 | 11 | laforge | h1. Iota (TWL3025) |
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| 2 | |||
| 3 | 1 | laforge | This is the Analog Baseband Chip TWL3025 |
| 4 | 2 | laforge | |
| 5 | 8 | laforge | It's very similar to its predecessors, the TWL3014 and TWL3016 devices. |
| 6 | |||
| 7 | A data sheet for the TWL3014 is available from http://www.52rd.com/bbs/Detail_RD.BBS_8719_68_1_1.html |
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| 8 | but forum registration is required for download. |
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| 9 | |||
| 10 | 7 | laforge | It consists of various functions, including |
| 11 | 10 | steve-m | * ADC and DAC for the GSM baseband signals |
| 12 | * ADC and DAC for the Voice/Audio path |
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| 13 | * DAC for APC (Automatic Power Control) |
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| 14 | * DAC for AFC (Automatic Frequency Control) |
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| 15 | * Battery Charging Controller |
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| 16 | * LDO's (Linear Power Regulators) |
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| 17 | 7 | laforge | |
| 18 | 1 | laforge | The functions of the ABB are controlled by a register set. The register set |
| 19 | 7 | laforge | is available through both USP and BSP. |
| 20 | |||
| 21 | |||
| 22 | 13 | laforge | h2. External Interfaces |
| 23 | |||
| 24 | h3. USP (uController Serial Port) |
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| 25 | 10 | steve-m | |
| 26 | 1 | laforge | This is the SPI-like control interface between DBB and the TWL3025 (ABB). |
| 27 | |||
| 28 | 12 | laforge | !twl3025_usp.png! |
| 29 | 1 | laforge | |
| 30 | |||
| 31 | 12 | laforge | h3. TSP (Time Serial Port) |
| 32 | 1 | laforge | |
| 33 | 10 | steve-m | |
| 34 | It is connected to the TSP controller inside the [[HardwareCalypso]] DBB. |
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| 35 | |||
| 36 | 9 | steve-m | The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: |
| 37 | 10 | steve-m | * CLK_13M is applied continuously to TWL3025 |
| 38 | * nTEN is in default state of high (inactive) |
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| 39 | * internal CLK6.5 is in default state low |
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| 40 | * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge |
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| 41 | * next CLK13M falling edge starts first CLK6.5 rising edge |
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| 42 | * every falling edge of CLK13M toggles CLK6.5 |
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| 43 | * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) |
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| 44 | * 7 bits are transferred during seven rising edges of CLK6.5 |
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| 45 | * TEN stays asserted for 1 CLK13M period after last bit is transferred |
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| 46 | * TEN needs to be released before next CLK13M rising edge to prevent another transfer |
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| 47 | 1 | laforge | |
| 48 | |||
| 49 | 10 | steve-m | h3. BSP (Baseband Serial Port) |
| 50 | 7 | laforge | |
| 51 | 10 | steve-m | |
| 52 | 12 | laforge | This synchronous serial port is connected to the RIF (Radio Inter Face) of the Calypso DBB. |
| 53 | 10 | steve-m | |
| 54 | |||
| 55 | h3. Debug traces |
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| 56 | |||
| 57 | 9 | steve-m | |
| 58 | 1 | laforge | The chip has very tiny debug traces on a small flex-pcb around the 4 sides of the chip. |
| 59 | Which trace goes to which ball can be seen on this scan: http://www.steve-m.de/pictures/iota_bottom.jpg |
