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laforge, 02/19/2016 10:48 PM

1 1 laforge
This is the Analog Baseband Chip TWL3025
2 2 laforge
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== TSP ==
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The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like:
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 * CLK_13M is applied continuously to TSL3025
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 * nTEN is in default state of high (inactive)
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 * internal CLK6.5 is in default state low
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 * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge
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 * next CLK13M falling edge starts first CLK6.5 rising edge
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 * every falling edge of CLK13M toggles CLK6.5
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 * TDR is sampled at every rising edge of CLK6.5 (including the first edge above)
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 * 7 bits are transferred during seven rising edges of CLK6.5
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 * TEN stays asserted for 1 CLK13M period after last bit is transferred
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 * TEN needs to be released before next CLK13M rising edge to prevent another transfer
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[[Image(Iota:twl3025_tsp_serial.png)]]
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