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Osmo-e1-xcvr » History » Version 10

laforge, 12/23/2017 01:57 PM

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h1.  osmo-e1-xcvr
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This is a simple hardware project that aims to generate a reusable module
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for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller
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projects.
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The board contains tranformers, the analog circuitry, the LIU (line interface
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unit), an oscillator as well as an integrated transceiver chip.
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It exposes the control interface (SPI) as well as the decoded synchronous
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Rx/Tx bitstreams each on a 2x5pin header.
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Framer, Multiplexe,r HDLC decoder or anything like that is out-of-scope for
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now.  The idea relaly is to provide an interface as low-level as possible.
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One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams
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are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC
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via USB.  The 2Mbps signal is very low-bandwidth, so that a pure software
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implementation should be absolutely no problem for todays computing power.
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h2. Status
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The project is in design phase.  Initial design has finished, but needs to be
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reviewed.  First prototype PCBs are evaluated since January 12, 2012
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h2. Hardware pictures
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h3. Bare PCB
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!{width:50%}osmo-e1-xcvr-pcb.jpg!
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h3. Populated PCB
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!{width:50%}osmo-e1-xcvr.jpg!
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h2. Hardware Documentation
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h3. JP2: TDM interface
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JP2 contains the serial TDM bitstream + clock for Rx and Tx direction.  The signals are
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||Pin||Name||Description||
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||1||GND||Ground||
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||2||nRST||low-active reset line, uC can reset the transceiver by pulling this low||
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||3||NC||||
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||4||LOS||Loss of Signal||
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||5||TDN||Transmit Data Negative||
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||6||RCLK||Receive Clock||
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||7||TD/TDP||Transmit Data / Transmit Data Positive||
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||8||RD/RDP||Receive Data / Receive Data Positive||
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||9||TCLK||Transmitter Clock.  Depending on JP9, this is an input into the board, or an output||
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||10||RDN/CV||Receive Data Negative / Code Violation||
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h3. JP1: SPI control
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This is how the external microcontroller can control the transceiver chip.
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||Pin||Name||Description||
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||1||VCC_IN||Vcc input, board can be supplied form here if SJ2 is closed||
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||2||GND||Ground||
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||3||NC||Not connected||
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||4||nINT||low-active interrupt output, when transceiver wants to interrupt uC""||
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||5||NC||Not connected||
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||6||NC||Not connected||
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||7||SDO||Serial Data Out (MISO)||
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||8||SDI||Serial Data In (MOSI)||
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||9||SCLK||Serial Clock||
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||10||nCS||low-active chip-select of the SPI||
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h3. JP9
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JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators
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of 2.048 MHz and 1.544 MHz.  This is required for selecting between E1 or T1/J1 mode.
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||1-2||2.048 MHz (E1) mode||
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||2-3||1.544 MHz (T1/J1) mode||
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h3. JP10
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This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock.
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||closed||use MCLK as TCLK source, TCLK pin on JP2 is output||
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||open||external circuit provides TCLK on JP2||
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h3. JP3 + JP4
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JP3can be used to supply power to the board.
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h2. show me the code
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http://cgit.osmocom.org/cgit/osmo-e1-xcvr/
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h2. TODO list
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* hardware
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** make ridiculously large test pads smaller
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** move C1 closer to U1 VDDIO pad (19)
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** remove $ sign from component names
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** define which value C5 should use
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** mark pin 1 of J1 / J2 on copper + silk screen
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** different footprint for L1 ?  value ?
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** JP10 is a big too close to J1
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* software
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** implement minimal SPI driver to initialize transceiver chip
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