Osmo-e1-xcvr » History » Version 6
laforge, 02/19/2016 10:48 PM
pcb pic
1 | 1 | laforge | [[PageOutline]] |
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2 | 1 | laforge | = osmo-e1-xcvr = |
3 | 1 | laforge | |
4 | 1 | laforge | This is a simple hardware project that aims to generate a reusable module |
5 | 1 | laforge | for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller |
6 | 1 | laforge | projects. |
7 | 1 | laforge | |
8 | 1 | laforge | The board contains tranformers, the analog circuitry, the LIU (line interface |
9 | 1 | laforge | unit), an oscillator as well as an integrated transceiver chip. |
10 | 1 | laforge | |
11 | 1 | laforge | It exposes the control interface (SPI) as well as the decoded synchronous |
12 | 1 | laforge | Rx/Tx bitstreams each on a 2x5pin header. |
13 | 1 | laforge | |
14 | 1 | laforge | Framer, Multiplexe,r HDLC decoder or anything like that is out-of-scope for |
15 | 1 | laforge | now. The idea relaly is to provide an interface as low-level as possible. |
16 | 1 | laforge | |
17 | 1 | laforge | One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams |
18 | 1 | laforge | are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC |
19 | 1 | laforge | via USB. The 2Mbps signal is very low-bandwidth, so that a pure software |
20 | 1 | laforge | implementation should be absolutely no problem for todays computing power. |
21 | 1 | laforge | |
22 | 1 | laforge | == Status == |
23 | 1 | laforge | |
24 | 1 | laforge | The project is in design phase. Initial design has finished, but needs to be |
25 | 5 | laforge | reviewed. First prototype PCBs are evaluated since January 12, 2012 |
26 | 5 | laforge | |
27 | 5 | laforge | == Hardware pictures == |
28 | 5 | laforge | |
29 | 5 | laforge | === Bare PCB === |
30 | 5 | laforge | |
31 | 5 | laforge | === Populated PCB === |
32 | 6 | laforge | [[Image(osmo-e1-xcvr-pcb.jpg, 50%)]] |
33 | 1 | laforge | |
34 | 1 | laforge | == Hardware Documentation == |
35 | 1 | laforge | |
36 | 1 | laforge | === JP2: TDM interface === |
37 | 1 | laforge | |
38 | 1 | laforge | JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are |
39 | 1 | laforge | ||Pin||Name||Description|| |
40 | 1 | laforge | ||1||GND||Ground|| |
41 | 1 | laforge | ||2||nRST||low-active reset line, uC can reset the transceiver by pulling this low|| |
42 | 1 | laforge | ||3||NC|||| |
43 | 1 | laforge | ||4||LOS||Loss of Signal|| |
44 | 1 | laforge | ||5||TDN||Transmit Data Negative|| |
45 | 1 | laforge | ||6||RCLK||Receive Clock|| |
46 | 1 | laforge | ||7||TD/TDP||Transmit Data / Transmit Data Positive|| |
47 | 1 | laforge | ||8||RD/RDP||Receive Data / Receive Data Positive|| |
48 | 1 | laforge | ||9||TCLK||Transmitter Clock. Depending on JP9, this is an input into the board, or an output |
49 | 1 | laforge | ||10||RDN/CV||Receive Data Negative / Code Violation|| |
50 | 1 | laforge | |
51 | 1 | laforge | === JP1: SPI control === |
52 | 1 | laforge | |
53 | 1 | laforge | This is how the external microcontroller can control the transceiver chip. |
54 | 1 | laforge | |
55 | 1 | laforge | ||Pin||Name||Description|| |
56 | 3 | laforge | ||1||VCC_IN||Vcc input, board can be supplied form here if SJ2 is closed|| |
57 | 3 | laforge | ||2||GND||Ground|| |
58 | 1 | laforge | ||3||NC||Not connected|| |
59 | 3 | laforge | ||4||nINT||low-active interrupt output, when transceiver wants to interrupt uC""|| |
60 | 1 | laforge | ||5||NC||Not connected|| |
61 | 3 | laforge | ||6||NC||Not connected|| |
62 | 3 | laforge | ||7||SDO||Serial Data Out (MISO)|| |
63 | 3 | laforge | ||8||SDI||Serial Data In (MOSI)|| |
64 | 3 | laforge | ||9||SCLK||Serial Clock|| |
65 | 3 | laforge | ||10||nCS||low-active chip-select of the SPI|| |
66 | 1 | laforge | |
67 | 1 | laforge | === JP9 === |
68 | 1 | laforge | |
69 | 1 | laforge | JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators |
70 | 1 | laforge | of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode. |
71 | 1 | laforge | |
72 | 1 | laforge | ||1-2||2.048 MHz (E1) mode|| |
73 | 1 | laforge | ||2-3||1.544 MHz (T1/J1) mode|| |
74 | 1 | laforge | |
75 | 1 | laforge | === JP10 === |
76 | 1 | laforge | |
77 | 1 | laforge | This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock. |
78 | 1 | laforge | |
79 | 1 | laforge | ||closed||use MCLK as TCLK source, TCLK pin on JP2 is output|| |
80 | 2 | laforge | ||open||external circuit provides TCLK on JP2|| |
81 | 1 | laforge | |
82 | 1 | laforge | === JP3 + JP4 === |
83 | 1 | laforge | |
84 | 3 | laforge | JP3can be used to supply power to the board. |
85 | 1 | laforge | |
86 | 1 | laforge | == show me the code == |
87 | 1 | laforge | |
88 | 1 | laforge | http://cgit.osmocom.org/cgit/osmo-e1-xcvr/ |
89 | 4 | laforge | |
90 | 4 | laforge | == TODO list == |
91 | 4 | laforge | * hardware |
92 | 4 | laforge | * make ridiculously large test pads smaller |
93 | 4 | laforge | * move C1 closer to U1 VDDIO pad (19) |
94 | 4 | laforge | * remove $ sign from component names |
95 | 4 | laforge | * define which value C5 should use |
96 | 4 | laforge | * mark pin 1 of J1 / J2 on copper + silk screen |
97 | 4 | laforge | * different footprint for L1 ? value ? |
98 | 4 | laforge | * JP10 is a big too close to J1 |
99 | 4 | laforge | * software |
100 | 4 | laforge | * implement minimal SPI driver to initialize transceiver chip |