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---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_clkgen.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Clock Management
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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library xp2;
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use xp2.all;
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use xp2.components.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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entity usbrx_clkgen is
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port(
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-- clock input
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clk_30_pclk : in std_logic; -- 30MHz
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ext_rst : in std_logic; -- external reset
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-- system clock
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clk_30 : out std_logic; -- 30MHz clock
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clk_80 : out std_logic; -- 80MHz clock
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rst_30 : out std_logic; -- 30MHz reset
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rst_80 : out std_logic -- 80MHz reset
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);
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end usbrx_clkgen;
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architecture rtl of usbrx_clkgen is
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-- reset generation
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signal rst_pll : std_logic; -- reset signal for PLLs
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signal pll_locked : std_logic; -- PLLs locked
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signal reset_i : std_logic; -- reset-signal
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-- system clock management
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signal clk_80_pll : std_logic;
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-- enusure that signal-names are kept (important for timing contraints)
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attribute syn_keep of clk_80_pll : signal is true;
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-- component declaration
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component EPLLD1
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generic (CLKOK_BYPASS : in String; CLKOS_BYPASS : in String;
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CLKOP_BYPASS : in String; DUTY : in Integer;
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PHASEADJ : in String; PHASE_CNTL : in String;
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CLKOK_DIV : in Integer; CLKFB_DIV : in Integer;
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CLKOP_DIV : in Integer; CLKI_DIV : in Integer;
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FIN : in String);
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port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
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RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic;
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DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
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DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
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DFPAI0: in std_logic; PWD: in std_logic; CLKOP: out std_logic;
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CLKOS: out std_logic; CLKOK: out std_logic; LOCK: out std_logic;
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CLKINTFB: out std_logic);
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end component;
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begin
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--
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-- reset generation
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--
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-- generate asynchronous reset-signal
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rg: entity mt_reset_gen
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port map (
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clk => clk_30_pclk,
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ext_rst => ext_rst,
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pll_locked => pll_locked,
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reset_pll => rst_pll,
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reset_sys => reset_i
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);
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-- sync reset to clock-domains
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rs30: entity mt_reset_sync
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port map (
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clk => clk_30_pclk,
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rst_in => reset_i,
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rst_out => rst_30
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);
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rs80: entity mt_reset_sync
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port map (
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clk => clk_80_pll,
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rst_in => reset_i,
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rst_out => rst_80
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);
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--
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-- system clock
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--
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-- PLL for system-clock
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pll : EPLLD1
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generic map (
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FIN => "30.0",
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CLKOK_BYPASS => "DISABLED",
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CLKOS_BYPASS => "DISABLED",
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CLKOP_BYPASS => "DISABLED",
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PHASE_CNTL => "STATIC",
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DUTY => 8,
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PHASEADJ => "0.0",
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CLKOK_DIV => 2,
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CLKOP_DIV => 8,
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CLKFB_DIV => 8,
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CLKI_DIV => 3
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)
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port map (
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CLKI => clk_30_pclk,
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CLKFB => clk_80_pll,
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RST => rst_pll,
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RSTK => '0',
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DPAMODE => '0',
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DRPAI3 => '0',
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DRPAI2 => '0',
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DRPAI1 => '0',
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DRPAI0 => '0',
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DFPAI3 => '0',
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DFPAI2 => '0',
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DFPAI1 => '0',
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DFPAI0 => '0',
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PWD => '0',
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CLKOP => clk_80_pll,
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CLKOS => open,
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CLKOK => open,
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LOCK => pll_locked,
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CLKINTFB=> open
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);
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-- output clocks
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clk_30 <= clk_30_pclk;
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clk_80 <= clk_80_pll;
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end rtl;
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