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---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_toplevel.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Toplevel component
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_toplevel is
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port (
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-- common
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clk_in_pclk : in std_logic;
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-- special control
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dings : in std_logic;
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dingsrst : in std_logic;
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-- ADC interface
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adc_cs : out std_logic;
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adc_sck : out std_logic;
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adc_sd1 : in std_logic;
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adc_sd2 : in std_logic;
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-- control SPI
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ctl_int : out std_logic;
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ctl_cs : in std_logic;
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ctl_sck : in std_logic;
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ctl_mosi : in std_logic;
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ctl_miso : out std_logic;
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-- data SPIs
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rx_clk : out std_logic;
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rx_syn : out std_logic;
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rx_dat : out std_logic;
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-- data SPIs
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tx_clk : in std_logic;
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tx_syn : in std_logic;
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tx_dat : in std_logic;
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-- gain PWMs
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gain0 : out std_logic;
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gain1 : out std_logic;
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-- GPS
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gps_1pps : in std_logic;
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gps_10k : in std_logic;
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-- gpios
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led : inout std_logic;
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gpio : inout std_logic_vector(9 downto 0);
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-- virtual GNDs/VCCs
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vgnd : out std_logic_vector(11 downto 0);
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vcc33 : inout std_logic_vector(11 downto 0);
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vcc12 : inout std_logic_vector(4 downto 0)
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);
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end usbrx_toplevel;
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architecture rtl of usbrx_toplevel is
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-- clocks
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signal clk_30 : std_logic;
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signal clk_80 : std_logic;
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signal rst_30 : std_logic;
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signal rst_80 : std_logic;
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-- config
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signal cfg_pwm : usbrx_pwm_config_t;
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signal cfg_gpio : usbrx_gpio_config_t;
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signal cfg_adc : usbrx_adc_config_t;
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signal cfg_ssc : usbrx_ssc_config_t;
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signal cfg_fil : usbrx_fil_config_t;
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signal cfg_off : usbrx_off_config_t;
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-- status
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signal stat_ref : usbrx_ref_status_t;
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signal stat_gpio : usbrx_gpio_status_t;
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-- ADC <-> offset
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signal adc_off_clk : std_logic;
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signal adc_off_i : unsigned(13 downto 0);
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signal adc_off_q : unsigned(13 downto 0);
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-- offset <-> filter
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signal off_fil_clk : std_logic;
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signal off_fil_i : signed(15 downto 0);
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signal off_fil_q : signed(15 downto 0);
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-- filter <-> output
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signal fil_out_clk : std_logic;
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signal fil_out_i : signed(15 downto 0);
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signal fil_out_q : signed(15 downto 0);
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-- enusure that signal-names are kept (important for timing contraints)
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attribute syn_keep of clk_in_pclk : signal is true;
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begin
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-- house-keeping
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cg: entity usbrx_clkgen
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port map (
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-- clock input
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clk_30_pclk => clk_in_pclk,
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ext_rst => dingsrst,
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-- system clock
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clk_30 => clk_30,
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clk_80 => clk_80,
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rst_30 => rst_30,
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rst_80 => rst_80
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);
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-- register bank
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rb: entity usbrx_regbank
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- config
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cfg_pwm => cfg_pwm,
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cfg_adc => cfg_adc,
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cfg_ssc => cfg_ssc,
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cfg_fil => cfg_fil,
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cfg_off => cfg_off,
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cfg_gpio => cfg_gpio,
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-- status
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stat_ref => stat_ref,
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stat_gpio => stat_gpio,
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-- SPI interface
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spi_ncs => ctl_cs,
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spi_sclk => ctl_sck,
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spi_mosi => ctl_mosi,
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spi_miso => ctl_miso
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);
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-- reference clock measurement
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refclk: entity usbrx_clkref
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port map (
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-- system clocks
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clk_sys => clk_80,
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rst_sys => rst_80,
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-- reference signal
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clk_ref => clk_30,
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rst_ref => rst_30,
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-- 1pps signal
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gps_1pps => gps_1pps,
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-- status
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status => stat_ref
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);
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-- GPIOs
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io: entity usbrx_gpio
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- GPIOs
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gpio(9 downto 0) => gpio,
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gpio(10) => led,
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-- config / status
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config => cfg_gpio,
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status => stat_gpio
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);
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-- gain PWMs
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pwm: entity usbrx_pwm
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- config
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config => cfg_pwm,
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-- PWM output
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pwm0 => gain0,
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pwm1 => gain1
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);
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-- A/D interface
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adc: entity usbrx_ad7357
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- config
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config => cfg_adc,
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-- ADC interface
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adc_cs => adc_cs,
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adc_sck => adc_sck,
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adc_sd1 => adc_sd1,
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adc_sd2 => adc_sd2,
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-- output
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out_clk => adc_off_clk,
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out_i => adc_off_i,
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out_q => adc_off_q
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);
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-- offset stage
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off: entity usbrx_offset
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- config
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config => cfg_off,
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-- input
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in_clk => adc_off_clk,
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in_i => adc_off_i,
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in_q => adc_off_q,
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-- output
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out_clk => off_fil_clk,
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out_i => off_fil_i,
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out_q => off_fil_q
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);
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-- decimation filter
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fil: entity usbrx_decimate
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- config
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config => cfg_fil,
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-- input
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in_clk => off_fil_clk,
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in_i => off_fil_i,
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in_q => off_fil_q,
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-- output
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out_clk => fil_out_clk,
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out_i => fil_out_i,
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out_q => fil_out_q
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);
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-- SSC output
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ssc: entity usbrx_ssc
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port map (
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-- common
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clk => clk_80,
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reset => rst_80,
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-- config
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config => cfg_ssc,
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-- output
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in_clk => fil_out_clk,
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in_i => fil_out_i,
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in_q => fil_out_q,
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-- SSC interface
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ssc_clk => rx_clk,
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ssc_syn => rx_syn,
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ssc_dat => rx_dat
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);
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-- drive unused IOs
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ctl_int <= '1';
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-- virtual GNDs/VCCs
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vgnd <= (others=>'0');
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vcc12 <= (others=>'Z');
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vcc33 <= (others=>'1');
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end rtl;
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