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---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_gpio.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : GPIO Block
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_gpio is
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port(
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- GPIOs
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gpio : inout std_logic_vector(10 downto 0);
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-- config / status
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config : in usbrx_gpio_config_t;
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status : out usbrx_gpio_status_t
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);
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end usbrx_gpio;
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architecture rtl of usbrx_gpio is
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-- register
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signal ireg : std_logic_vector(10 downto 0) := (others=>'0');
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signal oreg : std_logic_vector(10 downto 0) := (others=>'0');
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signal oena : std_logic_vector(10 downto 0) := (others=>'0');
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begin
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-- create output-driver
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od: for i in gpio'range generate
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begin
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gpio(i) <= oreg(i) when oena(i)='1' else 'Z';
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end generate;
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-- IOBs
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process(clk)
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begin
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if rising_edge(clk) then
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ireg <= to_X01(gpio);
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oreg <= config.odata;
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oena <= config.oena;
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end if;
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end process;
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end rtl;
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