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---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_regbank.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Registerbank
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_regbank is
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port(
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- config
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cfg_pwm : out usbrx_pwm_config_t;
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cfg_gpio : out usbrx_gpio_config_t;
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cfg_adc : out usbrx_adc_config_t;
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cfg_ssc : out usbrx_ssc_config_t;
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cfg_fil : out usbrx_fil_config_t;
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cfg_off : out usbrx_off_config_t;
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-- status
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stat_ref : in usbrx_ref_status_t;
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stat_gpio : in usbrx_gpio_status_t;
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-- SPI interface
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spi_ncs : in std_logic;
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spi_sclk : in std_logic;
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spi_mosi : in std_logic;
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spi_miso : out std_logic
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);
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end usbrx_regbank;
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architecture rtl of usbrx_regbank is
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-- bus interface
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signal bus_rena : std_logic;
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signal bus_wena : std_logic;
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signal bus_addr : unsigned(6 downto 0);
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signal bus_rdata : std_logic_vector(31 downto 0);
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signal bus_wdata : std_logic_vector(31 downto 0);
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-- registers
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signal reg_pwm1 : std_logic_vector(31 downto 0);
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signal reg_pwm2 : std_logic_vector(31 downto 0);
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signal reg_adc : std_logic_vector(15 downto 0);
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signal reg_ssc1 : std_logic_vector(0 downto 0);
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signal reg_ssc2 : std_logic_vector(7 downto 0);
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signal reg_fil : std_logic_vector(2 downto 0);
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signal reg_off : std_logic_vector(31 downto 0);
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signal reg_gain : std_logic_vector(31 downto 0);
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signal reg_swap : std_logic_vector(0 downto 0);
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signal reg_ioe : std_logic_vector(10 downto 0);
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signal reg_iod : std_logic_vector(10 downto 0);
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-- avoid block-ram inference
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attribute syn_romstyle : string;
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attribute syn_romstyle of rtl : architecture is "logic";
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begin
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-- SPI slave
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spi: entity usbrx_spi
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- SPI interface
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spi_ncs => spi_ncs,
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spi_sclk => spi_sclk,
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spi_mosi => spi_mosi,
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spi_miso => spi_miso,
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-- bus interface
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bus_rena => bus_rena,
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bus_wena => bus_wena,
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bus_addr => bus_addr,
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bus_rdata => bus_rdata,
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bus_wdata => bus_wdata
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);
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-- handle requests
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process(reset, clk)
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begin
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if reset = '1' then
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bus_rdata <= (others=>'0');
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reg_pwm1 <= x"17701F3F";
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reg_pwm2 <= x"07D01F3F";
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reg_adc <= x"0401";
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reg_ssc1 <= "0";
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reg_ssc2 <= x"01";
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reg_fil <= "011";
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reg_off <= x"00000000";
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reg_gain <= x"80008000";
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reg_swap <= "0";
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reg_ioe <= "00000000000";
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reg_iod <= "00000000000";
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elsif rising_edge(clk) then
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-- output zeros by default
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bus_rdata <= (others=>'0');
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-- handle requests
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case to_integer(bus_addr) is
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when 0 =>
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-- identification
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bus_rdata <= x"DEADBEEF";
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when 1 =>
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-- PWM #1
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bus_rdata <= reg_pwm1;
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if bus_wena='1' then
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reg_pwm1 <= bus_wdata(31 downto 0);
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end if;
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when 2 =>
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-- PWM #2
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bus_rdata <= reg_pwm2;
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if bus_wena='1' then
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reg_pwm2 <= bus_wdata(31 downto 0);
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end if;
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when 3 =>
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-- ADC interface
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bus_rdata <= to_slv32(reg_adc);
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if bus_wena='1' then
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reg_adc <= bus_wdata(15 downto 0);
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end if;
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when 4 =>
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-- SSC interface
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bus_rdata( 0 downto 0) <= reg_ssc1;
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bus_rdata(15 downto 8) <= reg_ssc2;
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if bus_wena='1' then
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reg_ssc1 <= bus_wdata( 0 downto 0);
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reg_ssc2 <= bus_wdata(15 downto 8);
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end if;
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when 5 =>
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-- <unused>
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null;
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when 6 =>
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-- decimation filter
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bus_rdata <= to_slv32(reg_fil);
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if bus_wena='1' then
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reg_fil <= bus_wdata(2 downto 0);
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end if;
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when 7 =>
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-- sample offset
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bus_rdata <= reg_off;
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if bus_wena='1' then
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reg_off <= bus_wdata(31 downto 0);
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end if;
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when 8 =>
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-- sample gain
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bus_rdata <= reg_gain;
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if bus_wena='1' then
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reg_gain <= bus_wdata(31 downto 0);
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end if;
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when 9 =>
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-- sample swap
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bus_rdata(0 downto 0) <= reg_swap;
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if bus_wena='1' then
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reg_swap <= bus_wdata( 0 downto 0);
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end if;
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when 10 =>
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-- GPIO - output enable
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bus_rdata(10 downto 0) <= reg_ioe;
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if bus_wena='1' then
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reg_ioe <= bus_wdata(10 downto 0);
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end if;
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when 11 =>
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-- GPIO - output data
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bus_rdata(10 downto 0) <= reg_iod;
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if bus_wena='1' then
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reg_iod <= bus_wdata(10 downto 0);
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end if;
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when 12 =>
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-- GPIO - input data
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bus_rdata(10 downto 0) <= stat_gpio.idata;
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when 13 =>
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-- reference frequency
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bus_rdata(24 downto 0) <= std_logic_vector(stat_ref.lsb);
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bus_rdata(31 downto 25) <= std_logic_vector(stat_ref.msb);
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when others =>
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-- invalid address
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null;
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end case;
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end if;
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end process;
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-- map registers to config
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cfg_pwm.freq0 <= unsigned(reg_pwm1(15 downto 0));
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cfg_pwm.freq1 <= unsigned(reg_pwm2(15 downto 0));
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cfg_pwm.duty0 <= unsigned(reg_pwm1(31 downto 16));
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cfg_pwm.duty1 <= unsigned(reg_pwm2(31 downto 16));
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cfg_adc.clkdiv <= unsigned(reg_adc( 7 downto 0));
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cfg_adc.acqlen <= unsigned(reg_adc(15 downto 8));
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cfg_ssc.tmode <= reg_ssc1(0);
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cfg_ssc.clkdiv <= unsigned(reg_ssc2);
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cfg_fil.decim <= unsigned(reg_fil);
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cfg_fil.decim <= unsigned(reg_fil);
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cfg_off.ioff <= signed(reg_off(15 downto 0));
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cfg_off.qoff <= signed(reg_off(31 downto 16));
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cfg_off.igain <= unsigned(reg_gain(15 downto 0));
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cfg_off.qgain <= unsigned(reg_gain(31 downto 16));
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cfg_off.swap <= reg_swap(0);
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cfg_gpio.oena <= reg_ioe;
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cfg_gpio.odata <= reg_iod;
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end rtl;
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