ISDN Chips » History » Revision 29
Revision 28 (WIMPy, 03/05/2024 12:23 PM) → Revision 29/63 (WIMPy, 03/05/2024 12:50 PM)
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ISDN Chips |_.Vendor|_.Name|_.Interface|_.PCM highway|_.Host Interface|_.Extras|.Datasheet| |AMD|Am79C30A Am79C32A|1 BRI S/T|SBP, IOM2|bus8:3||attachment:"Am79C30A Am79C32A DSC vG data sheet [1995-01].pdf" attachment:"Am79C30A Am79C32A DSC vH data sheet [1998-12].pdf"| |Cologne Chip|HFC-4S Chip Design|HFC-4S HFC-8S|8 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-8S-4S.pdf"| |Cologne Chip|HFC-E1|1 Chip Design|HFC-E1|1 E1 HDB3/AMI|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-E1.pdf"| |Cologne Chip|HFC-S Chip Design|HFC-S PCI|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-S PCI.pdf"| |Cologne Chip|HFC-S Chip Design|HFC-S PCI A|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-S PCI A.pdf"| |Cologne Chip|HFC-S Chip Design|HFC-S active|1 BRI S/T TE/LT|MST, IOM2|(internal)|ARM7 based SoC|attachment:"HFC-S-active.pdf" attachment:"product-brief-eval-board-HFC-s-active.pdf"| |Cologne Chip|HFC-S Chip Design|HFC-S mini|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-S-mini.pdf"| |Cologne Chip|HFC-S Chip Design|HFC-S USB|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-S USB.pdf"| |Cologne Chip|HFC-S|1 Chip Design|HFC-S|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-S.pdf"| |Cologne Chip|HFC-SP|1 Chip Design|HFC-SP|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-SP.pdf"| |Cologne Chip|HFC-S+|1 Chip Design|HFC-S+|1 BRI S/T TE/LT|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-S+.pdf"| |Cologne Chip|HFC-U|(none)|MST, Chip Design|HFC-U|(none)|MST, IOM2|bus8/16/32:8/16 busX32 SPI||attachment:"HFC-U.pdf"| |Cologne Chip|XHFC-1SU|1 Chip Design|XHFC-1SU|1 BRI (either S/T or Up) TE/LT|MST, IOM2|bus8:1 busX8 SPI||attachment:"XHFC-1SU.pdf"| |Cologne Chip|XHFC-2S4U|4 Chip Design|XHFC-2S4U|4 BRI 2 (either S/T or Up) + 2 Up TE/LT|MST, IOM2|bus8:1 busX8 SPI||attachment:"XHFC-2S4U-4SU.pdf"| |Cologne Chip|XHFC-2SU|2 Chip Design|XHFC-2SU|2 BRI (either S/T or Up) TE/LT|MST, IOM2|bus8:1 busX8 SPI||attachment:"XHFC-2SU.pdf" attachment:"XHFC-2SU-evalboard.pdf"| |Cologne Chip|XHFC-4SU|4 Chip Design|XHFC-4SU|4 BRI (either S/T or Up) TE/LT|MST, IOM2|bus8:1 busX8 SPI||attachment:"XHFC-2S4U-4SU.pdf" attachment:"XHFC-4SU-evalboard.pdf"| |Lucent|T7234|2 BRI 1 Uk(2B1Q) + 1 S/T |(none)|pins|Single Chip NT|attachment:"T7234 Data Sheet Advisory [1998-11].pdf"| |Lucent|T7237||||| |Lucent|T7250||||| |Lucent|T7256|2 BRI 1 Uk(2B1Q) + 1 S/T |2048|pins|Single Chip NT|attachment:"T7256 Data Sheet Advisory [1998-11].pdf"| |Lucent|T7259||||| |Lucent|T7903 ISA-MWAC|3 BRI S/T TE/LT|CHI|bus8/6:3||attachment:"T7903 ISA-MWAC [1997-04].pdf"| |Motorola|MC145474 MC145475|1 BRI S/T TE/LT|IDL|pins||attachment:"MC145474 MC145475 ISDN ST Interface Tranceiver [1992].pdf"| |ST|ST5420 SID-µW|1 BRI S/T TE/LT|DSI 256 512 2048 2560|Microwire||attachment:"ST5420 ST Interface [1992-04].pdf"| |ST|ST5451|(none)|IOM2, DSI 2048 4096|bus8:6 busX8||attachment:"ST5451 ISDN HDLC AND GCI Controller [2000-03].pdf"| |ST|STLC5411|1 BRI Uk(2B1Q) LT/NT|IOM2, DSI|Microwire||attachment:"STLC5411 2B1Q Interface [1995-11].pdf" attachment:"STLC5411 2B1Q Interface [1996-11].pdf" attachment:"STLC5411 2B1Q Interface [2003-09].pdf"| |National Semiconductor|TP3420|1 BRI S/T TE/LT|DSI|Microwire||attachment:"TP3420A datasheet [1994-07].pdf" attachment:"TP3420 S Interface Device (SID) Users Guides noa821.pdf" attachment:"TP3420A Appnotes snoa823 Line Interface Circuit Considerations [1994-07].pdf"| |National Semiconductor|TP3421|1 BRI S/T TE/LT|IOM2|||attachment:"TP3420 S Interface Device (SID) Users Guides noa821.pdf"| |Mitel Zarlink|MT8930B SNIC|1 BRI S/T TE/LT|Mitel ST-Bus 2048|busX8||attachment:"MT8930B [1993-08].pdf"| |Mitel Zarlink|MT8931C SNIC|1 BRI S/T TE/LT|Mitel ST-Bus 2048|busX8||attachment:"MT8931C [1997-11].pdf"| |Mitel Zarlink|MT8979|1 E1 HDB3/AMI|Mitel ST-Bus 2048|||attachment:"MT8979 CEPT PCM30 CRC-4 Framer & Interface [1995-05].pdf" attachment:"MT8979 CEPT PCM30 CRC-4 Framer & Interface [2005-02].pdf"| |VLSI|ACTIS|1 BRI S/T TE/??|IOM2|(internal)|ARM based SoC|attachment:"ACTIS v1.0 overview [1997-10].pdf"| |VLSI|VNS80000B VIPem|1 BRI S/T TE/??|IOM2|(internal)|ARM7 based SoC with analogue frontend|attachment:"VNS80000 VIP v1.0 overview [1997-10].pdf" attachment:"VNS80000B VIPem v2.5 data sheet [1997-09].pdf"| |Yamaha|YM7405B IDNDCH|1 BRI S/T|(none)|bus8/16:15||attachment:"YM7405B IDNDCH ISDN basic access interface [1996-01].pdf"| |Siemens|PEB 2025 IEPC|4* any|-|bus4:2||attachment:"PEB 2025 IEPC (ISDN Exchange Power Controller) general description [1983].pdf" attachment:"PEB 2025 IEPC (ISDN Exchange Power Controller) preliminary data [1900].pdf" attachment:"PEB 2025 IEPC (ISDN Exchange Power Controller) data sheet [1992-05].pdf"| |Siemens|PEB 2026 IHPC|1* any|-|-||attachment:"PEB 2026 IHPC (ISDN High Voltage Power Controller) general description [1983].pdf"| |Siemens|PEB 20320 MUNICH32|(none)|1536 1544 2048 4096|bus32:30||attachment:"PEB 20320 MUNICH32 (Multichannel Network Interface Controller for HDLC) general description [1983].pdf"| |Siemens|PEB 2035 ACFA|(none)|2048 4096|bus8:4||attachment:"PEB 2035 ACFA (Advanced CMOS Frame Aligner) general description [1983].pdf" attachment:"PEB 2035 ACFA (Advanced CMOS Frame Aligner) preliminary data [1990].pdf" attachment:"PEB 2035 ACFA (Advanced CMOS Frame Aligner) data sheet [1994-01].pdf"| |Siemens|PEB 2045 MTSC PEF 2045 MTSC|4* 2048|4* 2048 4096 8192|bus8:1||attachment:"PEB 2045 MTSC (Memory Time Switch CMOS) general description.pdf" attachment:"PEB 2045 MTSC (Memory Time Switch CMOS) preliminary data [1990].pdf" attachment:"PEB 2045 MTSC (Memory Time Switch CMOS) preliminary data sheet [1994-01].pdf"| |Siemens|PEB 2046 MTSS PEF 2046 MTSS|(none)|8* 256|bus8:1||attachment:"PEB 2046 MTSS (Memory Time Switch Small) general description.pdf" attachment:"PEB 2046 MTSS (Memory Time Switch Small) preliminary data [1990].pdf"| |Siemens|PEB 2047 MTSL PEF 2047-16 MTSL-16|(none)|8* 2048|bus8:1||attachment:"PEB 2047 MTSL (Memory Time Switch Large) general description [1983].pdf"| |Siemens|PEB 2050 PBC|8 codec|2* 512|bus8:0 DMA||attachment:"PEB 2050 PBC (Peripferal Board Controller) preliminary data [1990].pdf"| |Siemens|PEB 2052 PIC|8 codec|2* 512|bus8:0 DMA||attachment:"PEB 2052 PIC (PCM Interface Controller) general description.pdf" attachment:"PEB 2052 PIC (PCM Interface Controller) preliminary data [1990].pdf"| |Siemens|PEB 2054 EPIC-S|16|2* <=8192 2*<=4096|busX8|64 ch switch|attachment:"PEB 2054 EPIC-S (Extended PCM Interface Controller - Small) general description [1983].pdf"| |Siemens|PEB 2055 EPIC-1|(none)|8* SLD 2* IOM2, IOM1, SLD PCM <=8192 4* 2048 4096 8192|bus8:3 busX8|128 ch switch|attachment:"PEB 2055 EPIC-1 (Extended PCM Interface Controller) general description.pdf" attachment:"PEB 2055 EPIC-1 (Extended PCM Interface Controller) preliminary data [1990].pdf"| |Siemens|PEB 20550 ELIC|(none)|4* IOM2, IOM1, SLD PCM 4* 8192|bus DMA||attachment:"PEB 2056 EPIC-2 (Extended PCM Interface Controller) preliminary data [1990].pdf"|