Auerswald COMmander Basic2 Electronics » History » Version 6
laforge, 02/20/2022 02:48 PM
1 | 1 | laforge | h1. Auerswald COMmander Basic2 Electronics |
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3 | h2. Mainboard |
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5 | 5 | laforge | As we can see, there are the following main components: |
6 | * StrongARM processor with SDRAM (2x Samsung K4S281632I-UC75) + Flash (ST NAND512W3A2BN6) |
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7 | ** this is where the [[Linux_on_Auerswald_Commander_Basic_2]] runs |
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8 | ** StrongARM peripheral: IC+ IP101A Ethernet PHY |
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9 | * TI TMS320VC5501 DSP with its own RAM (ISSI IS61LV641G-10TL) |
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10 | * Lattice LFEC1E programmable logic for interfacing with the bus/backplane |
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11 | * various smaller bus latches/drivers |
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14 | 1 | laforge | {{thumbnail(Auerswald_COMB2_mainboard1.jpg)}} |
15 | {{thumbnail(Auerswald_COMB2_mainboard2.jpg)}} |
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16 | {{thumbnail(Auerswald_COMB2_mainboard_detail.jpg)}} |
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18 | h2. 8 S0 Module |
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20 | 3 | laforge | As can be seen clearly on the picutre, it uses the [[CologneChip_HFC|CologneChip HFC-8S]] 8-port S/T interface IC. There's a lattice glue logic chip for interfacing with the backplane bus, and the analog frontend + magnetics sections for 8 ports. Four ports have jumper blocks to change the NT/TE cross-over, while the other 4 ports are static. |
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22 | 2 | laforge | {{thumbnail(Auerswald_COMmander_8S0_top.jpg)}} |
23 | {{thumbnail(Auerswald_COMmander_8S0_bottom.jpg)}} |
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25 | 1 | laforge | h2. 4 S0 Module |
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27 | 6 | laforge | This is basically just a partially populated 8S0 module, using a [[CologneChip_HFC|HFC-4S]] chip instead of the HFC-8S. |
28 | 2 | laforge | |
29 | {{thumbnail(Auerswald_COMmander_4S0.jpg)}} |
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30 | {{thumbnail(Auerswald_COMmander_4S0_top.jpg)}} |
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31 | {{thumbnail(Auerswald_COMmander_4S0_bottom.jpg)}} |
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33 | 1 | laforge | h2. 8 a/b Module |
34 | 6 | laforge | |
35 | This is a design around the following two Infineon PEB 2466H _SICOFI4-µC Four Channel Codec Filter with PCM and Microcontroller Interface_, datasheet at attachment:"PEB,PEF 2466 Hardware Ref Manual.pdf" |
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37 | The bus glue / attachment is done with discrete logic using chips of the 74HCxxx series. |
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39 | The analog line interface features |
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40 | * MC34074 operational amplifier, datasheet at attachment:MC34071-D.PDF |
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41 | * MOC3023X opto-coupler with triac output, datasheet at attachment:MOC3023X.pdf |
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42 | 1 | laforge | |
43 | 2 | laforge | {{thumbnail(Auerswald_COMmander_8ab_top.jpg)}} |
44 | {{thumbnail(Auerswald_COMmander_9ab_bottom.jpg)}} |
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45 | {{thumbnail(Auerswald_COMmander_8ab.jpg)}} |
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47 | 1 | laforge | h2. S2M Module |
48 | 2 | laforge | |
49 | 4 | laforge | The S2M (PRI) module is centered around an Infineon PEF2256E FALC56 chip. This is one of the most common E1 framers on the market. |
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51 | The glue logic for interfacing with the backplane/bus is implemented in a Xilinx CPLD. |
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52 | |||
53 | 2 | laforge | {{thumbnail(Auerswald_COMmander_S2M_top.jpg)}} |
54 | {{thumbnail(Auerswald_COMmander_S2m_bottom.jpg)}} |